Semiconductor-on-insulator (SOI) devices are increasingly employed in high performance integrated circuits for superior performance to bulk semiconductor devices. As the operating frequency of integrated circuits exceeds 1 gigahertz (GHz) with continued scaling of semiconductor devices, on-chip capacitors having a large capacitance are increasingly relied upon to maintain reliable functionality of high frequency integrated circuits. For example, decoupling capacitors are widely used in state-of-the art high frequency integrated circuits to suppress a voltage fluctuation in a power supply network during high speed switching operations. Another exemplary application of on-chip capacitors is the emerging system-on-chip (SoC) technology in which digital, analog, and passive semiconductor devices are integrated on the same chip to provide enhanced functionality. A small fluctuation in voltage or current of an electrical signal in such circuits may cause severe performance degradation, or even detrimental system malfunction. Using on-chip capacitors as a charge reservoir can prevent or minimize such undesired signal fluctuations.
Several prior art methods are known for fabricating capacitors with a high capacitance on an SOI substrate. In one prior art method, a conventional planar capacitor is employed in which the capacitance of the planar capacitor is increased by simply increasing the area of the capacitor. This method has the advantage of incurring a low processing cost because planar capacitors can be fabricated simultaneously with logic devices by using a conventional CMOS processing sequence. However, a large surface area is occupied by these planar capacitors, resulting in a low device density and a large chip size, which decreases chip yield and may eventually increase cost if a large number of planar capacitors are employed in the integrated circuit.
Another prior art method provides deep trench capacitors, which enable a high-capacitance without requiring a large surface area. The deep trench capacitors employ deep trenches formed in a semiconductor substrate prior to formation of standard complementary metal oxide semiconductor (CMOS) devices. Methods of forming deep trench capacitors are well known in the art. Co-assigned U.S. Pat. No. 6,057,188 to El-Kareh et al. and U.S. Pat. Nos. 5,770,875 and 5,759,907 to Assaderaghi et al., which provide deep trench capacitors on an SOI substrate and methods of manufacturing the same, are incorporated herein by reference.
Although deep trench capacitors have the advantage of providing high capacitance capacitors at a high areal density, this approach has several disadvantages that limit its application primarily to DRAM (Dynamic Random Access Memory) products. First, forming deep trench capacitors requires a significant number of complicated and costly processing steps such as etching of deep trenches in a semiconductor substrate, forming buried capacitor plates, filling the deep trenches, etc. Most of these processing steps are unique to deep trench technology, and thus, incompatible with conventional SOI CMOS processing sequence for logic devices such as a processor core. Second, processing steps for manufacturing deep trenches increase total processing time for semiconductor chips, and consequently, increase the time-to-market of products employing deep trench capacitors. Finally, this approach is costly because expensive equipment and heavy investment in research and development are required for the development deep trench related processes.
In view of the above, there exists a need for a high capacitance capacitor compatible with a semiconductor-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processing sequence, and methods of manufacturing the same without significantly increasing process complexity or cost.